Fractional gates come to Heron's instruction set architecture

Related blog: New fractional gates reduce circuit depth for utility-scale workloads

Today IBM Quantum™ announces the addition of a new feature as well as the removal of an old one. Starting with ibm_torino, new basis gates will be added to the Heron Instruction Set Architecture (ISA) over the next two weeks. These fractional gates offer continuously parameterized single-qubit (rx) and two-qubit (rzz) instructions implemented with a single control pulse.

With rx gates, all single-qubit rotations (u3) can be achieved with a single control pulse, rather than being decomposed into two sx gates and three rz gates. This reduces the duration and error for single-qubit gates by up to a factor of two.

Similarly, rzz gates eliminate a decomposition into multiple cz gates for a common operation in time evolution circuits.

These new gates are not compatible with some of the existing technology for error mitigation and dynamic circuits in Qiskit Runtime. Support for optimizing circuits to take advantage of rzz gates within the Qiskit SDK transpiler is also limited. Consequently, users must opt-in to receive a backend object that includes these fractional gates in the backend Target. Please see the documentation for more information.

Adding such fractional gates to the ISA of IBM Quantum processors was the predominant use case described by users for pulse-level control. Now that support for these gates is built-in, pulse-level control on all IBM Quantum processors is deprecated and will be removed on 3 February 2025. The pulse module is also scheduled for removal in Qiskit SDK v2.0. If you have been using pulse-level support to investigate optimal control techniques, check out the qiskit-dynamics package repo and its documentation to facilitate ongoing numerical investigations.