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Optimize for target hardware

All Qiskit pattern steps are shown (Map problem, Optimize for hardware, Execute on hardware, and Post-process results). The 'Optimize for hardware' step is emphasized.  This step uses the Qiskit SDK and the Qiskit Transpiler Service.

In the "optimize for target hardware" step of a Qiskit pattern, you take the abstract circuits (or operators) produced from the map step and perform a series of optimizations on them. This can include mapping the route and layout of the circuit to physical qubit hardware, converting to basis gates of the hardware, and reducing the number of operations, all designed to optimize the likelihood of success in the later execute step. At this point you might also wish to debug your circuits with a simulator before executing on real hardware in the next step.

During this step, abstract circuits must be transpiled to Instruction Set Architecture (ISA) circuits. An ISA circuit is one that only consists of gates understood by the target hardware (basis gates), and any multi-qubit gates needed to obey any connectivity constraints (coupling map). Only ISA circuits can be run on IBM® hardware using IBM Qiskit Runtime.


Guides for optimizing for target hardware

Get started with the Qiskit transpiler

Configure preset pass managers

Advanced transpilation resources

Qiskit transpiler service

Debugging tools

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