Allocate all idle nodes from the coupling map or target as ancilla on the layout.
A pass for allocating all idle physical qubits (those that exist in coupling map or target but not the dag circuit) as ancilla. It will also choose new virtual qubits to correspond to those physical ancilla.
This is an analysis pass, and only responsible for choosing physical ancilla locations and their corresponding virtual qubits. A separate transformation pass must add those virtual qubits to the circuit.
Check if the pass is an analysis pass.
If the pass is an AnalysisPass, that means that the pass can analyze the DAG and write the results of that analysis in the property set. Modifications on the DAG are not allowed by this kind of pass.
Check if the pass is a transformation pass.
If the pass is a TransformationPass, that means that the pass can manipulate the DAG, but cannot modify the property set (but it can be read).
execute(passmanager_ir, state, callback=None)
Execute optimization task for input Qiskit IR.
- passmanager_ir (Any (opens in a new tab)) – Qiskit IR to optimize.
- state (PassManagerState) – State associated with workflow execution by the pass manager itself.
- callback (Callable (opens in a new tab) | None) – A callback function which is caller per execution of optimization task.
Optimized Qiskit IR and state of the workflow.
Name of the pass.
Run the FullAncillaAllocation pass on dag.
Extend the layout with new (physical qubit, virtual qubit) pairs. The dag signals which virtual qubits are already in the circuit. This pass will allocate new virtual qubits such that no collision occurs (i.e. Layout bijectivity is preserved)
The coupling_map and layout together determine which physical qubits are free.
dag (DAGCircuit) – circuit to analyze
returns the same dag circuit, unmodified
TranspilerError – If there is not layout in the property set or not set at init time.
Update workflow status.
- state (PassManagerState) – Pass manager state to update.
- run_state (RunState) – Completion status of current task.
Updated pass manager state.
static validate_layout(layout_qubits, dag_qubits)
Checks if all the qregs in layout_qregs already exist in dag_qregs. Otherwise, raise.