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ConstrainedReschedule

class qiskit.transpiler.passes.ConstrainedReschedule(*args, **kwargs)

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Bases: AnalysisPass

Rescheduler pass that updates node start times to conform to the hardware alignments.

This pass shifts DAG node start times previously scheduled with one of the scheduling passes, e.g. ASAPScheduleAnalysis or ALAPScheduleAnalysis, so that every instruction start time satisfies alignment constraints.

Examples

We assume executing the following circuit on a backend with 16 dt of acquire alignment.

     ┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├
     └───┘└────────────────┘└╥┘
c: 1/════════════════════════╩═
                             0

Note that delay of 100 dt induces a misalignment of 4 dt at the measurement. This pass appends an extra 12 dt time shift to the input circuit.

     ┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├
     └───┘└────────────────┘└╥┘
c: 1/════════════════════════╩═
                             0

Notes

Your backend may execute circuits violating these alignment constraints. However, you may obtain erroneous measurement result because of the untracked phase originating in the instruction misalignment.

Create new rescheduler pass.

The alignment values depend on the control electronics of your quantum processor.

Parameters

  • acquire_alignment – Integer number representing the minimum time resolution to trigger acquisition instruction in units of dt.
  • pulse_alignment – Integer number representing the minimum time resolution to trigger gate instruction in units of dt.
  • target – The Target representing the target backend, if target is specified then this argument will take precedence and acquire_alignment and pulse_alignment will be ignored.

Attributes

is_analysis_pass

Check if the pass is an analysis pass.

If the pass is an AnalysisPass, that means that the pass can analyze the DAG and write the results of that analysis in the property set. Modifications on the DAG are not allowed by this kind of pass.

is_transformation_pass

Check if the pass is a transformation pass.

If the pass is a TransformationPass, that means that the pass can manipulate the DAG, but cannot modify the property set (but it can be read).

Methods

execute

execute(passmanager_ir, state, callback=None)

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Execute optimization task for input Qiskit IR.

Parameters

  • passmanager_ir (Any) – Qiskit IR to optimize.
  • state (PassManagerState) – State associated with workflow execution by the pass manager itself.
  • callback (Callable | None) – A callback function which is caller per execution of optimization task.

Returns

Optimized Qiskit IR and state of the workflow.

Return type

tuple[Any, qiskit.passmanager.compilation_status.PassManagerState]

name

name()

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Name of the pass.

Return type

str

run

run(dag)

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Run rescheduler.

This pass should perform rescheduling to satisfy:

  • All DAGOpNode nodes (except for compiler directives) are placed at start time satisfying hardware alignment constraints.
  • The end time of a node does not overlap with the start time of successor nodes.

Assumptions:

  • Topological order and absolute time order of DAGOpNode are consistent.
  • All bits in either qargs or cargs associated with node synchronously start.
  • Start time of qargs and cargs may different due to I/O latency.

Based on the configurations above, the rescheduler pass takes the following strategy:

  1. The nodes are processed in the topological order, from the beginning of

    the circuit (i.e. from left to right). For every node (including compiler directives), the function _push_node_back performs steps 2 and 3.

  2. If the start time of the node violates the alignment constraint,

    the start time is increased to satisfy the constraint.

  3. Each immediate successor whose start_time overlaps the node’s end_time is

    pushed backwards (towards the end of the wire). Note that at this point the shifted successor does not need to satisfy the constraints, but this will be taken care of when that successor node itself is processed.

  4. After every node is processed, all misalignment constraints will be resolved,

    and there will be no overlap between the nodes.

Parameters

dag (DAGCircuit) – DAG circuit to be rescheduled with constraints.

Raises

TranspilerError – If circuit is not scheduled.

update_status

update_status(state, run_state)

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Update workflow status.

Parameters

  • state (PassManagerState) – Pass manager state to update.
  • run_state (RunState) – Completion status of current task.

Returns

Updated pass manager state.

Return type

PassManagerState

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